8086 Pins and Signals

Real-world analogy

What is it?

The 8086 microprocessor uses a 40-pin DIP package where each pin serves a specific role: AD0-AD15 carry multiplexed address and data, A16-A19 provide upper address bits, ALE latches the address, RD/WR control read and write operations, M/IO distinguishes memory from I/O access, INTR/NMI handle interrupts, HOLD/HLDA enable DMA, READY inserts wait states for slow devices, and RESET initializes the processor.

Real-world relevance

Every PC motherboard ever made routes these exact signal types between the CPU and chipset. When your computer boots, the RESET pin releases and the CPU fetches its first instruction from address FFFF0h — this is why the BIOS ROM must sit at the top of the first megabyte. Understanding these pins is essential for designing embedded 8086 systems and reading hardware schematics.

Key points

• 40-Pin DIP Package — The 8086 comes in a 40-pin Dual Inline Package. Every pin has a specific purpose — address, data, control, power, or ground. Understanding each pin is essential for hardware interfacing and reading timing diagrams.
• AD0–AD15: Multiplexed Address/Data Bus — Pins AD0 through AD15 carry address bits A0-A15 during T1 (first clock cycle) and data bits D0-D15 during T2-T4. This multiplexing saves pins but requires an external latch (like 8282) to hold the address.
• A16/S3–A19/S6: High Address and Status — Pins A16-A19 provide the upper 4 bits of the 20-bit address during T1. During T2-T4, these pins output status signals S3-S6 that indicate which segment register is being used and interrupt enable status.
• ALE — Address Latch Enable — ALE is a pulse output by the 8086 at the start of every bus cycle (during T1). External latches like the 8282 capture the address on the falling edge of ALE, holding it stable while the bus switches to carrying data.
• RD and WR — Read and Write Strobes — RD (active low) signals that the CPU wants to read data from memory or I/O. WR (active low) signals a write operation. These control lines tell external devices when to place data on the bus or capture data from it.
• M/IO — Memory or I/O Select — When M/IO is HIGH, the current bus cycle accesses memory. When LOW, it accesses an I/O port. This single pin tells the system whether the address on the bus refers to a memory location or a peripheral device.
• INTR and NMI — Interrupt Inputs — INTR (maskable interrupt) can be enabled or disabled via the IF flag using STI/CLI. NMI (Non-Maskable Interrupt) cannot be disabled — it always interrupts the CPU. NMI is used for critical events like memory parity errors.
• HOLD and HLDA — DMA Handshake — A DMA controller asserts HOLD to request the bus. The 8086 finishes its current bus cycle, floats its bus lines (tri-state), and asserts HLDA (Hold Acknowledge). The DMA controller now owns the bus for direct memory transfers.
• READY — Wait State Control — The READY pin is sampled at the start of T3. If LOW, the CPU inserts wait states (Tw) — extra clock cycles where it does nothing — until READY goes HIGH. This lets slow memory or peripherals keep up with the faster CPU.
• RESET — System Initialization — When RESET is held HIGH for at least 4 clock cycles and then released, the 8086 initializes: CS=FFFFh, IP=0000h, all flags cleared, DS=ES=SS=0000h. Execution begins at physical address FFFF0h — the reset vector.
• MN/MX — Mode Selection — Pin 33 (MN/MX) selects the operating mode. Tied to VCC = minimum mode (single processor, CPU generates control signals directly). Tied to GND = maximum mode (multiprocessor, 8288 bus controller generates control signals).

Code example

; Visualizing an 8086 memory read bus cycle
; Step-by-step pin activity during a MOV AX, [2000h]

; T1 state:
;   ALE = HIGH (address is valid)
;   AD0-AD15 = 2000h (lower 16 bits of address)
;   A16-A19  = segment-derived upper bits
;   M/IO     = HIGH (memory access)

; T1 falling edge of ALE:
;   External 8282 latch captures address 2000h

; T2 state:
;   ALE = LOW
;   AD0-AD15 = floating (tri-state), preparing for data
;   RD = LOW (read strobe asserted)

; T3 state:
;   READY sampled — if LOW, insert Tw
;   AD0-AD15 = data from memory appears

; T4 state:
;   CPU latches data from AD0-AD15 into AX
;   RD = HIGH (read complete)
;   Bus cycle ends

Line-by-line walkthrough

1. 1. T1 state: ALE goes HIGH — this is the 'address is ready!' announcement. AD0-AD15 carry the 16-bit address of the memory location we want to read.
2. 2. A16-A19 carry the upper 4 address bits derived from the segment register — together with AD0-AD15, this forms the full 20-bit physical address.
3. 3. M/IO is set HIGH because this is a memory access (MOV from memory), not an I/O port operation.
4. 4. On the falling edge of ALE, external 8282 latches capture and hold the address — the bus is about to switch roles.
5. 5. T2 state: AD0-AD15 go tri-state momentarily, then RD is asserted LOW — this tells the memory chip to place its data on the bus.
6. 6. T3 state: the CPU checks the READY pin — if the memory is slow and READY is LOW, the CPU just waits in Tw states.
7. 7. Once READY is HIGH, the memory has placed valid data on AD0-AD15. The CPU reads these lines.
8. 8. T4 state: the CPU captures the data into the destination register (AX), releases RD back to HIGH, and the bus cycle is complete.

Spot the bug

; System design: 8086 connected to memory
; Problem: Data read from memory is always garbage

; Hardware setup:
;   AD0-AD15 connected directly to memory data pins
;   A16-A19 connected to upper address decoder
;   RD connected to memory OE (output enable)
;   ALE is not connected to anything
;   M/IO connected to memory CS (chip select)

Explain like I'm 5

Fun fact

Hands-on challenge

More resources

• 8086 Pin Diagram and Description (GeeksforGeeks)
• 8086 Pins and Signals Explained (YouTube)
• Intel 8086 Datasheet (Intel)
• 8086 Bus Cycle and Timing (TutorialsPoint)