Lesson 37 of 48 intermediate

Memory Interfacing with RAM and ROM

Connecting the CPU to Its Storage

Open interactive version (quiz + challenge)

Real-world analogy

Imagine a post office with numbered PO boxes. The CPU is the mail carrier who knows every box number (address). ROM boxes are locked glass cases — you can read the mail inside but never change it. RAM boxes have doors you can open to read or replace mail. Address decoding is like the sorting machine that routes each letter to the correct wing of the post office.

What is it?

Memory interfacing is the process of connecting RAM and ROM chips to the 8086 CPU so it can read instructions from ROM and read/write data in RAM. It involves address decoding (using logic gates or decoder ICs like 74LS138) to generate chip select signals, mapping memory chips to specific address ranges, and handling the 16-bit data bus with even/odd bank organization.

Real-world relevance

Every computer, phone, and embedded device uses memory interfacing. Your PC's BIOS is stored in ROM mapped at the top of address space — just like the 8086. RAM modules in your laptop use far more complex decoding, but the principle of chip selection and address mapping is identical to what we learn here.

Key points

Why Memory Interfacing Matters — The 8086 CPU needs external memory chips to store programs (ROM) and data (RAM). Interfacing means wiring these chips so the CPU can read/write the correct locations. Without proper interfacing, the CPU would talk to the wrong chip or get garbage data — like dialing a wrong phone number.
Address Decoding — Full vs Partial — Full decoding uses ALL address lines to select a chip, giving each chip a unique, non-overlapping range. Partial decoding ignores some high-order lines — simpler hardware but the same chip appears at multiple (shadow) addresses. Full decoding is preferred in production systems; partial is fine for small trainers.
Chip Select (CS) Logic — Every memory chip has a Chip Select (CS) pin — active LOW. The chip only responds when CS is asserted (pulled to 0). Address decoding logic combines upper address bits through gates or decoders to generate CS for each chip. If CS is HIGH, the chip ignores the bus entirely — its outputs go to high-impedance (tri-state).
ROM Mapping — Program Storage — ROM (Read-Only Memory) stores the boot code and fixed programs. In 8086, the reset vector is at FFFF0h, so ROM must be mapped to the top of the 1MB address space. Common ROM chips: 2764 (8KB), 27128 (16KB), 27256 (32KB). ROM has only OE (Output Enable) — no WE, since you cannot write to it during normal operation.
RAM Mapping — Data Storage — RAM (Random Access Memory) stores variables, stack, and runtime data. It is read/write, so both OE and WE pins are used. Common SRAM chips: 6264 (8KB), 62256 (32KB). RAM is typically placed starting at low addresses (00000h). For 16-bit 8086, you often need two RAM chips — one for even bytes (D0-D7) and one for odd bytes (D8-D15) — selected by A0 and BHE.
Using a 2-to-4 Decoder (74LS139) — A 2-to-4 decoder takes 2 input lines and activates 1 of 4 outputs (active LOW). Feed two upper address bits to the inputs, and each output becomes a chip select for a different memory block. The 74LS139 contains two independent 2-to-4 decoders — very handy for simple memory maps with up to 4 chips per decoder.
3-to-8 Decoder (74LS138) for Larger Maps — The 74LS138 is a 3-to-8 decoder — 3 inputs select 1 of 8 active-LOW outputs. It also has 3 enable pins (G1 active HIGH, G2A and G2B active LOW). By connecting upper address lines to inputs and using enables for additional address bits, you can decode up to 8 memory regions cleanly with one chip.
Memory Map Design — A memory map is a diagram showing which address ranges are assigned to which chips. Good design places ROM at the top (for reset vector), RAM at the bottom (for interrupt vectors and data), and I/O in between. Always check for overlaps and gaps. Draw the map before wiring — it is the blueprint of your system.
Even/Odd Bank Architecture for 16-bit Bus — The 8086 has a 16-bit data bus but memory chips are 8-bit. So memory is organized as two banks: the even bank (A0=0, data on D0-D7) and the odd bank (BHE=0, data on D8-D15). A byte read at an even address uses only the even bank. A byte at an odd address uses the odd bank. A word read activates both banks simultaneously.

Code example

; =============================================
; Memory Interface: 8KB ROM + 8KB RAM for 8086
; =============================================
;
; ROM (2764): mapped at FE000h - FFFFFh
; RAM (6264): mapped at 00000h - 01FFFh
;
; --- ROM Address Decoding ---
; A19=1, A18=1, A17=1, A16=1, A15=1, A14=1, A13=1
; CS_ROM = NAND(A19,A18,A17,A16,A15,A14,A13)
;
; ROM connections:
;   A0-A12  → ROM address pins
;   D0-D7   → ROM data pins
;   RD      → ROM OE (Output Enable)
;   CS_ROM  → ROM CE (Chip Enable)
;
; --- RAM Address Decoding ---
; A19=0, A18=0, A17=0, A16=0, A15=0, A14=0, A13=0
; CS_RAM = NOR(A19,A18,A17,A16,A15,A14,A13)
;
; RAM connections:
;   A0-A12  → RAM address pins
;   D0-D7   → RAM data pins
;   RD      → RAM OE
;   WR      → RAM WE (Write Enable)
;   CS_RAM  → RAM CE
;
; Verification:
;   MOV AL, [0000h]  ; reads from RAM ✓
;   JMP FFFF0h       ; executes from ROM ✓

Line-by-line walkthrough

1. Title comment for our memory interface design
2. Describing the system: 8KB ROM and 8KB RAM connected to 8086
3. Blank separator
4. ROM chip 2764 will live at addresses FE000h through FFFFFh (top 8KB)
5. RAM chip 6264 will live at addresses 00000h through 01FFFh (bottom 8KB)
6. Blank separator
7. Starting ROM address decoding section
8. For FE000h-FFFFFh, address bits A19 through A13 must all be 1
9. NAND gate: output goes LOW (active) only when all inputs are HIGH
10. Blank separator
11. ROM wiring: CPU address lines A0-A12 connect to ROM address pins
12. ROM data pins connect to CPU data bus D0-D7
13. CPU RD signal connects to ROM Output Enable — read activates data output
14. The decoded chip select connects to ROM Chip Enable pin
15. Blank separator
16. Starting RAM address decoding section
17. For 00000h-01FFFh, address bits A19 through A13 must all be 0
18. NOR gate: output goes HIGH inverted to LOW (active) when all inputs are 0
19. Blank separator
20. RAM wiring: same A0-A12 to RAM address pins
21. RAM data pins connect to D0-D7
22. RD signal to RAM OE for read operations
23. WR signal to RAM WE for write operations — RAM is read/write unlike ROM
24. Decoded chip select to RAM CE pin
25. Blank separator
26. Verification section
27. Reading from address 0000h hits RAM — confirmed by decoding
28. Reset jump to FFFF0h executes from ROM — confirmed by decoding

Spot the bug

; Memory decoding for ROM at F0000-FFFFF (64KB)
; Using 74LS138 decoder
;
; C=A19, B=A18, A=A17
; G1=Vcc, G2A=A16, G2B=GND
;
; ROM connected to output Y7
; Y7 active when CBA = 111 and G2A = 0
;
; So ROM is selected when:
;   A19=1, A18=1, A17=1, A16=0
;   Address range: E0000h - EFFFFh

Need a hint?

Check what address A19=1, A18=1, A17=1, A16=0 actually represents. Does it match F0000-FFFFF?

Show answer

The decoding selects E0000h-EFFFFh, NOT F0000h-FFFFFh. When A16=0 (required for G2A active LOW), the range starts at E0000h. To select F0000h-FFFFFh, G2A should be connected to NOT(A16), so G2A=0 when A16=1. Alternatively, use A16 through an inverter before connecting to G2A.

Explain like I'm 5

Think of the CPU as a librarian in a huge library. The library has two sections: a 'read-only' section (ROM) where books are behind glass — you can look but not change them — and a 'read-write' section (RAM) where you can borrow, return, and even scribble notes. Address decoding is like the sign at each aisle telling the librarian which section and shelf to go to based on the book number.

Fun fact

The original IBM PC used a 74LS138 decoder to divide its 1MB address space into 8 blocks of 128KB each. This single cheap chip was the traffic controller for the entire memory system — routing every memory access to the correct chip. The 74LS138 is still manufactured today and costs about 50 cents.

Hands-on challenge

Design a memory map for an 8086 system with 32KB ROM at the top of memory and 64KB RAM at the bottom. Draw the address ranges, determine which address lines to decode, and specify the logic (gates or decoder) needed for chip select generation. Verify that the reset vector falls within your ROM range.

More resources

8086 Memory Interfacing (Neso Academy)
Address Decoding Techniques (GeeksforGeeks)
74LS138 Decoder Datasheet (Texas Instruments)
Memory Map Design for 8086 (Education 4u)

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