8255 Programmable Peripheral Interface

Real-world analogy

What is it?

The 8255 PPI is a programmable parallel I/O chip that provides 24 I/O lines organized as three 8-bit ports (A, B, C). It supports three operating modes: Mode 0 (simple I/O), Mode 1 (strobed I/O with handshaking), and Mode 2 (bidirectional bus on Port A). A control word written to its control register configures port directions and modes. BSR mode allows individual Port C bits to be set or reset.

Real-world relevance

The 8255 was used in the original IBM PC to interface the keyboard, read DIP switch settings, and control the speaker. Many university microprocessor lab kits still include the 8255 for hands-on experiments. The concept of programmable I/O ports lives on in modern microcontrollers — every GPIO port on an Arduino or STM32 is a descendant of the 8255's design philosophy.

Key points

• 8255 Overview and Purpose — The 8255 PPI (Programmable Peripheral Interface) is a general-purpose parallel I/O chip by Intel. It provides 24 I/O pins organized into three 8-bit ports (A, B, C), configurable as input or output via software. It bridges the CPU to external devices like keyboards, LEDs, displays, motors, and sensors — without requiring custom hardware for each device.
• Pin Diagram and Bus Interface — The 8255 connects to the CPU via an 8-bit data bus (D0-D7), two address lines (A0-A1) to select the internal register, RD and WR for read/write, CS (chip select) for activation, and RESET. The 24 I/O pins connect to the external world. A0-A1 select which port to access: 00=Port A, 01=Port B, 10=Port C, 11=Control Register.
• Mode 0 — Simple Input/Output — Mode 0 is the most basic operating mode. Each port is configured as either all-input or all-output — no handshaking, no interrupts. Data written to an output port stays on the pins until changed. Data read from an input port captures whatever logic levels are on the pins at that instant. Port C can be split: upper nibble (PC4-7) and lower nibble (PC0-3) configured independently.
• Control Word Format — Bit by Bit — The 8255 control word is an 8-bit value written to the control register (base+3). Bit 7=1 means 'mode set' operation. Bits 6-5 select Mode for Group A (00=Mode 0, 01=Mode 1, 1x=Mode 2). Bit 4 sets Port A direction (1=input, 0=output). Bit 3 sets Port C upper direction. Bit 2 selects Mode for Group B (0=Mode 0, 1=Mode 1). Bit 1 sets Port B direction. Bit 0 sets Port C lower direction.
• Mode 1 — Strobed Input/Output — Mode 1 adds handshaking signals for synchronized data transfer. For input: the external device places data on the port and pulses STB (strobe) to latch it. The 8255 sets IBF (Input Buffer Full) and optionally raises INTR to interrupt the CPU. For output: the CPU writes data, the 8255 asserts OBF (Output Buffer Full), and the device pulses ACK when it takes the data. Port C pins are used for these handshaking signals.
• Mode 2 — Bidirectional Bus (Port A Only) — Mode 2 is available only for Port A. It provides bidirectional data transfer with full handshaking — Port A can both send and receive data on the same 8 lines. Five Port C lines (PC3-PC7) are dedicated to handshaking signals (STB, IBF, OBF, ACK, INTR). This mode is used when two systems need to pass data back and forth through the same port, like a shared bus between two processors.
• BSR (Bit Set/Reset) Mode — BSR mode lets you set or reset individual bits of Port C without affecting other bits. Write to the control register with bit 7=0 and encode which bit (0-7) to set or reset. This is extremely useful for controlling handshaking signals or toggling individual control lines without a read-modify-write cycle on the entire port.
• 8255 Interfacing Example — Complete Setup — A typical setup: connect 8255 to the 8086 at I/O base address 80h. Configure Port A as output (drive LEDs), Port B as input (read switches), Port C as output (control signals). Write the control word, then use IN/OUT instructions to communicate with the external devices through the 8255 ports.
• Address Decoding for 8255 — The 8255 needs a chip select (CS) generated by decoding the I/O address. For base address 80h (10000000b), decode A7=1 and A6-A2=0. Lines A0 and A1 pass through to the 8255's A0-A1 pins to select the internal register. The M/IO signal must be LOW (I/O cycle). A simple NAND gate or 74LS138 decoder can generate CS.

Code example

; =============================================
; 8255 PPI — Complete Configuration Example
; =============================================
;
; System: 8255 at I/O base 80h
;   Port A (80h) → Output to LEDs
;   Port B (81h) → Input from DIP switches
;   Port C (82h) → Mixed control signals
;   Control (83h)
;
; Step 1: Configure 8255
; Control word: Mode 0, PA=out, PB=in,
;              PCupper=out, PClower=in
; Bits: 1 00 0 0 0 1 1 = 83h
;
  MOV AL, 83h           ; control word
  OUT 83h, AL           ; write to control register
;
; Step 2: Read DIP switches (Port B)
  IN AL, 81h            ; AL = switch pattern
;
; Step 3: Process and display
  NOT AL                ; invert pattern
  OUT 80h, AL           ; write to LEDs (Port A)
;
; Step 4: Set a flag on Port C bit 0
  MOV AL, 01h           ; BSR: set PC0
  OUT 83h, AL           ; PC0 = 1 (flag active)
;
; Step 5: Read Port C lower nibble
  IN AL, 82h            ; read all of Port C
  AND AL, 0Fh           ; mask upper nibble
;
; Loop: continuously read switches, update LEDs
SCAN:
  IN AL, 81h            ; read switches
  OUT 80h, AL           ; mirror to LEDs
  JMP SCAN              ; repeat forever

Line-by-line walkthrough

1. 1. Title comment for 8255 configuration example
2. 2. Separator line
3. 3. Blank line
4. 4. System description: 8255 base address is 80h
5. 5. Port A at address 80h is configured as output driving LEDs
6. 6. Port B at address 81h is configured as input reading DIP switches
7. 7. Port C at address 82h provides mixed control signals
8. 8. Control register is at address 83h
9. 9. Blank line
10. 10. Step 1: Configure the 8255 by writing the control word
11. 11. Control word breakdown: Mode 0 for all, PA=out, PB=in, PCu=out, PCl=in
12. 12. Binary: 10000011 = 83h
13. 13. Blank line
14. 14. Load control word 83h into AL register
15. 15. Write AL to control register at port 83h — 8255 is now configured
16. 16. Blank line
17. 17. Step 2: Read the DIP switch positions from Port B
18. 18. IN instruction reads 8 switch bits into AL
19. 19. Blank line
20. 20. Step 3: Process the data and send to display
21. 21. NOT inverts all bits — turns switch pattern into LED pattern
22. 22. OUT sends the inverted pattern to Port A LEDs
23. 23. Blank line
24. 24. Step 4: Use BSR mode to set a flag on Port C
25. 25. Value 01h in BSR format: bit7=0, bit select=000, set=1 → sets PC0
26. 26. Writing to control register with bit7=0 triggers BSR mode
27. 27. Blank line
28. 28. Step 5: Read Port C and isolate lower nibble
29. 29. IN reads all 8 bits of Port C
30. 30. AND with 0Fh masks off the upper 4 bits, keeping only PC0-PC3
31. 31. Blank line
32. 32. Label SCAN for continuous polling loop
33. 33. Read current switch states from Port B
34. 34. Write switch states directly to LEDs on Port A
35. 35. Jump back to SCAN — infinite loop mirrors switches to LEDs

Spot the bug

; Configure 8255 at base 80h:
;   Port A = input, Port B = output, Mode 0
;
  MOV AL, 90h          ; control word
  OUT 80h, AL          ; send to control register
;
; Read from Port A:
  IN AL, 80h
;
; Write to Port B:
  MOV AL, 55h
  OUT 81h, AL

Explain like I'm 5

Fun fact

Hands-on challenge

More resources

• 8255 PPI Explained (Neso Academy)
• 8255 Programmable Peripheral Interface (GeeksforGeeks)
• Intel 8255A Datasheet (Intel)
• 8255 Mode 0, 1, 2 with Examples (Education 4u)