8237 DMA Controller

Real-world analogy

What is it?

The 8237 DMA Controller enables peripheral devices to transfer data directly to/from memory without CPU involvement. It has 4 channels, each with address and count registers. When a device asserts DREQ, the 8237 requests the bus from the CPU (HRQ/HLDA), then autonomously generates addresses and control signals to move data. It supports single, block, demand, and cascade transfer modes, freeing the CPU for other tasks during bulk data movement.

Real-world relevance

Every modern computer uses DMA extensively. When you copy a large file, the disk controller uses DMA to move data to RAM without CPU intervention. Your sound card uses DMA to stream audio samples. Network cards use DMA to receive packets. Modern DMA controllers are far more capable than the 8237 (scatter-gather lists, virtual addresses), but the fundamental concept — letting hardware move data without the CPU — is identical.

Key points

• What is DMA and Why Is It Needed? — DMA (Direct Memory Access) allows peripheral devices to transfer data directly to/from memory without the CPU executing instructions for each byte. Without DMA, the CPU must execute IN/OUT and MOV for every byte — using 100% of its time during large transfers (like reading a disk sector of 512 bytes). With DMA, the CPU just sets up the transfer and goes back to computing while the 8237 handles the data movement.
• 8237 Architecture — 4 DMA Channels — The 8237 has 4 independent DMA channels (CH0-CH3). Each channel has: a 16-bit address register (current address), a 16-bit count register (bytes remaining), and a page register (external, provides upper address bits). The 8237 also contains a command register, mode registers, status register, mask register, and request register for controlling operations.
• DREQ, DACK, HRQ, and HLDA Signals — The DMA handshake uses four key signals. DREQ (DMA Request): the peripheral asserts this to request a transfer. DACK (DMA Acknowledge): the 8237 responds, telling the device its channel is active. HRQ (Hold Request): the 8237 asks the CPU to release the bus. HLDA (Hold Acknowledge): the CPU grants the bus to the 8237. Only after HLDA does the 8237 take control of address and data buses.
• Transfer Modes — Single, Block, Demand, Cascade — Single Transfer: one byte per DREQ, CPU gets the bus back between bytes. Block Transfer: once started, transfers all N bytes without releasing the bus — fastest but blocks the CPU entirely. Demand Transfer: transfers as long as DREQ is active; if DREQ drops, the 8237 releases the bus and resumes when DREQ returns. Cascade: used to chain 8237s for more channels.
• Transfer Types — Read, Write, Verify — The 8237 supports three transfer types. Write transfer: data moves from I/O device to memory (device → memory). Read transfer: data moves from memory to I/O device (memory → device). Verify transfer: the 8237 generates addresses but no actual data transfer occurs — used for testing. Naming convention: 'read' and 'write' are from memory's perspective.
• Programming the 8237 — Register Setup — To program a DMA transfer: (1) Write the mode register for the channel. (2) Clear the byte pointer flip-flop (ensures LSB-first order). (3) Write the start address (LSB then MSB) to the address register. (4) Write the count minus 1 (LSB then MSB) to the count register. (5) Write the page register (upper address bits). (6) Unmask the channel. The 8237 is now armed and will begin when DREQ is asserted.
• Page Registers and 64KB Boundaries — The 8237 has only 16-bit address registers, addressing 64KB. To access the full 8086 address space (1MB), external page registers supply the upper 4 address bits (A16-A19). A DMA transfer CANNOT cross a 64KB page boundary — if it does, the address wraps around within the same page instead of incrementing to the next. Programmers must ensure buffers do not straddle a 64KB boundary.
• IBM PC DMA Usage — The IBM PC has two 8237 chips. The first (ports 00h-0Fh) handles 8-bit channels 0-3: CH0 for DRAM refresh, CH2 for floppy disk. The second 8237 (ports C0h-DFh) handles 16-bit channels 5-7: CH5/6/7 for ISA peripherals. CH4 is used for cascading the two 8237s. Sound Blaster cards typically use CH1 for 8-bit audio DMA. The floppy controller's DMA channel 2 is why floppy access feels seamless even on slow CPUs.

Code example

; =============================================
; 8237 DMA — Floppy Disk Read Setup
; =============================================
;
; Transfer 512 bytes from floppy to memory at 1000h
; Using DMA Channel 2 (IBM PC floppy channel)
;
; Disable DMA channel 2 during setup:
  MOV AL, 06h           ; mask CH2 (04h + 02h)
  OUT 0Ah, AL           ; single mask register
;
; Set mode: single transfer, write (device→mem), CH2
  MOV AL, 46h           ; 01 0 0 01 10
  OUT 0Bh, AL           ; mode register
;
; Clear byte pointer flip-flop:
  MOV AL, 00h
  OUT 0Ch, AL           ; resets LSB/MSB toggle
;
; Set start address = 1000h:
  MOV AL, 00h           ; address LSB
  OUT 04h, AL           ; CH2 address register
  MOV AL, 10h           ; address MSB
  OUT 04h, AL
;
; Set count = 511 (transfers 512 bytes):
  MOV AL, 0FFh          ; count LSB (01FFh)
  OUT 05h, AL           ; CH2 count register
  MOV AL, 01h           ; count MSB
  OUT 05h, AL
;
; Set page register = 0 (physical page 0):
  MOV AL, 00h
  OUT 81h, AL           ; CH2 page register
;
; Enable DMA channel 2:
  MOV AL, 02h           ; unmask CH2
  OUT 0Ah, AL
;
; DMA is armed!
; Now send 'read sector' command to floppy controller
; FDC will assert DREQ2 for each byte
; 8237 handles the entire 512-byte transfer
; CPU is FREE to do other work
; When done: TC asserted → interrupt via IRQ6

Line-by-line walkthrough

1. 1. Title comment for floppy disk DMA setup
2. 2. Separator line
3. 3. Blank line
4. 4. Description: transfer 512 bytes from floppy to memory address 1000h
5. 5. Using DMA Channel 2, which is the standard IBM PC floppy channel
6. 6. Blank line
7. 7. First, disable (mask) CH2 so we can safely modify its registers
8. 8. 06h = mask bit set + channel 2 selection
9. 9. Write to single mask register at port 0Ah
10. 10. Blank line
11. 11. Set the transfer mode for CH2
12. 12. 46h = single transfer, write (I/O to memory), channel 2
13. 13. Write to mode register at port 0Bh
14. 14. Blank line
15. 15. Clear the byte pointer flip-flop to ensure next write goes to LSB first
16. 16. Any value written to port 0Ch clears the flip-flop
17. 17. Write to clear flip-flop register
18. 18. Blank line
19. 19. Set the starting memory address to 1000h
20. 20. First write LSB = 00h to CH2 address register at port 04h
21. 21. Write LSB
22. 22. Then write MSB = 10h
23. 23. Write MSB — CH2 will start transferring to address 1000h
24. 24. Blank line
25. 25. Set byte count to 511 (8237 transfers count+1 bytes, so 511+1=512)
26. 26. LSB of 511 (01FFh) is FFh
27. 27. Write LSB to CH2 count register at port 05h
28. 28. MSB is 01h
29. 29. Write MSB — 8237 will transfer 512 bytes total
30. 30. Blank line
31. 31. Set the page register for physical address bits A16-A19
32. 32. Address 1000h is in page 0 (A19-A16 = 0000)
33. 33. Write to CH2 page register at port 81h
34. 34. Blank line
35. 35. Enable CH2 by clearing its mask bit
36. 36. 02h = unmask channel 2
37. 37. Write to single mask register — DMA is now armed and ready
38. 38. Blank line
39. 39. Comment: 8237 is waiting for DREQ2 from floppy controller
40. 40. Comment: send read command to FDC to start the disk operation
41. 41. Comment: FDC asserts DREQ2 each time a byte is ready
42. 42. Comment: 8237 handles the complete transfer autonomously
43. 43. Comment: CPU is free to execute other code during the transfer
44. 44. Comment: terminal count triggers IRQ6 to notify CPU of completion

Spot the bug

; DMA CH1 transfer 256 bytes to address 2000h
;
  MOV AL, 45h          ; mode: single, write, CH1
  OUT 0Bh, AL
;
  OUT 0Ch, AL          ; clear flip-flop
;
  MOV AL, 00h
  OUT 02h, AL          ; CH1 addr LSB
  MOV AL, 20h
  OUT 02h, AL          ; CH1 addr MSB
;
  MOV AL, 00h          ; count = 256
  OUT 03h, AL          ; CH1 count LSB
  MOV AL, 01h
  OUT 03h, AL          ; CH1 count MSB
;
  MOV AL, 01h
  OUT 0Ah, AL          ; unmask CH1

Explain like I'm 5

Fun fact

Hands-on challenge

More resources

• DMA Controller 8237 Explained (Neso Academy)
• 8237 DMA Controller (GeeksforGeeks)
• Intel 8237A Datasheet (Intel)
• How DMA Works in Computers (Education 4u)