Capstone: Trace, Explain, and Present a Full Interfaced System

Real-world analogy

What is it?

This capstone lesson brings together every concept from the entire course. You will trace complete system operations — from CPU instruction execution through address decoding, memory access, peripheral interaction, interrupt handling, and DMA transfer. You will analyze exam-style problems that combine knowledge across multiple topics. And you will practice presenting a complete system design: block diagram, memory map, decoding logic, initialization firmware, ISR code, and main application — the full skill set of a microprocessor engineer.

Real-world relevance

The ability to trace a complete system — to follow a signal from a device through an interrupt controller to the CPU, through the ISR, to a memory write, and out to a display — is exactly what embedded systems engineers do when debugging real products. When a car's ABS module fails, an engineer traces the sensor signal through the interrupt chain to find the fault. When a medical device misbehaves, engineers trace bus activity with logic analyzers. This complete-system thinking is the most valuable skill you can develop.

Key points

• What 'Trace the System' Means — Tracing a system means following the exact sequence of events from power-on to a specific operation: which address appears on the bus, which chip responds, what data flows, which signals are asserted, and in what order. It is the ultimate demonstration of understanding — you cannot fake a trace. If you can trace the complete execution of an instruction including address decoding, memory access, and peripheral interaction, you truly understand how a microprocessor system works.
• Tracing a Complete I/O Operation — Tracing an I/O port access (like OUT 80h, AL) follows the same logic but with M/IO=0. The address bus carries the port number (0080h), M/IO goes LOW signaling I/O, the I/O decoder generates CS_8255, and the 8255 latches the data from the data bus. Every signal change has a purpose, and exam questions often ask you to list them in order.
• Tracing an Interrupt Sequence — The most complex trace: a hardware interrupt from 8254 timer through 8259 PIC to the CPU. The timer counts to zero → asserts OUT0 → connected to 8259 IR0 → 8259 asserts INTR → CPU finishes current instruction → sends two INTA pulses → 8259 provides vector → CPU reads IVT → jumps to ISR → ISR executes → sends EOI → IRET. This involves every major chip in the system working together.
• Tracing a DMA Transfer — When the floppy controller wants to transfer data via DMA Channel 2: FDC asserts DREQ2 → 8237 asserts HRQ → CPU asserts HLDA → 8237 takes bus control → 8237 drives address bus and asserts DACK2 → data moves from FDC to memory → count decrements → when count=0, TC asserted → 8237 releases HRQ → CPU resumes. The CPU is completely hands-off during the actual transfer.
• Exam-Style Analysis Questions — University exams and interviews test your ability to analyze unfamiliar systems. Common formats: (1) Given a memory map, determine address ranges and decoder equations. (2) Given a control word, determine chip configuration. (3) Given assembly code, trace register and flag changes. (4) Given a system diagram, identify missing connections. (5) Calculate timing values for timer modes. You must combine knowledge from multiple lessons to answer these.
• Signal Timing Diagram Reading — Timing diagrams show signal values (HIGH/LOW) on a shared time axis. Being able to read them is essential for hardware understanding. Key signals to track: CLK (reference), ALE (address latch), Address Bus, Data Bus, RD/WR, M/IO, INTA, READY. Practice reading: when does the address appear? When does data become valid? When does the CPU latch data? These details matter for real hardware design.
• Design Presentation — Communicating Your Work — Presenting a system design means organizing your work for others: (1) System overview and requirements. (2) Block diagram showing all components. (3) Detailed memory and I/O map. (4) Address decoding equations with truth tables. (5) Complete initialization code with comments. (6) ISR code for each interrupt source. (7) Main loop flow. (8) Testing methodology. Good engineers communicate designs clearly — a brilliant design nobody can understand is a failed design.
• Course Synthesis — Everything Connects — This entire 48-lesson course flows as one integrated knowledge graph: digital logic (Lesson 4) builds gates used in decoders (Lesson 37). Registers (Lesson 11) hold data moved by instructions (Lessons 21-24). Addressing modes (Lesson 17) select memory interfaced in Lesson 37. Interrupts (Lessons 34-35) are managed by the 8259 (Lesson 42). Timers (Lesson 41) trigger those interrupts. I/O (Lessons 38-40) uses the 8255. Serial (Lesson 44) extends communication. Everything connects.

Code example

; =============================================
; CAPSTONE: Full System Trace Example
; =============================================
;
; Scenario: User presses key '5' on keyboard.
; Trace the COMPLETE path through the system.
;
; === PHASE 1: Key Detection ===
;
; Main loop executes: IN AL, 81h (read 8255 Port B)
;
; CPU bus cycle:
;   Address bus = 0081h
;   M/IO = 0 (I/O cycle)
;   I/O decoder: A7=1,A6=0,A5=0 → Y4 → CS_8255
;   8255: A1=0, A0=1 → Port B selected
;   CPU asserts RD
;   8255 puts Port B data on D0-D7
;   CPU reads into AL: 11011111 → column 5 active
;
; === PHASE 2: Display Update ===
;
; Code: MOV AL, [SEG_TABLE + 5]
;   CPU reads address 0000:SEG_TBL+5 from RAM
;   CS_RAM active (memory, low address)
;   AL = 6Dh (pattern for '5')
;
; Code: OUT 80h, AL
;   Address bus = 0080h, M/IO = 0
;   CS_8255 active, A1=0, A0=0 → Port A
;   CPU asserts WR, 8255 latches 6Dh
;   Seven-segment shows '5'
;
; === PHASE 3: Serial Logging ===
;
; Code: OUT 60h, AL (send '5' via 8251)
;   Address bus = 0060h, M/IO = 0
;   CS_8251 active
;   8251 serializes byte: START-10100110-STOP
;   TxD line sends at 9600 baud
;
; === PHASE 4: Timer Interrupt ===
;
; Meanwhile, 8254 Counter 0 reaches 0
;   OUT0 → 8259 IR0 → INTR asserted
;   CPU: INTA pulse 1 → ISR bit set
;   CPU: INTA pulse 2 → vector 08h received
;   CPU: reads IVT[08h] → jumps to TIMER_ISR
;   ISR: refreshes multiplexed display
;   ISR: MOV AL, 20h / OUT 20h, AL → EOI
;   ISR: IRET → back to main loop
;
; COMPLETE TRACE: keypress → detection → display
;   → serial log → timer interrupt → display refresh
;   All chips working together! ✓

Line-by-line walkthrough

1. 1. Title comment for the capstone full system trace
2. 2. Separator line
3. 3. Blank line
4. 4. Scenario description: user presses key '5' and we trace everything
5. 5. Blank line
6. 6. PHASE 1: Key Detection — scanning the keyboard through 8255
7. 7. Blank line
8. 8. Main loop reads Port B: IN AL, 81h
9. 9. Blank line
10. 10. CPU places port address 0081h on the address bus
11. 11. M/IO signal = 0 because this is an I/O instruction (IN)
12. 12. I/O decoder analyzes: A7=1, A6=0, A5=0 maps to output Y4
13. 13. Y4 drives CS_8255 LOW — the 8255 is selected
14. 14. Inside the 8255: A1=0, A0=1 selects Port B register
15. 15. CPU asserts RD (read) control signal
16. 16. 8255 responds by placing Port B data onto D0-D7 of the data bus
17. 17. CPU reads the data bus into AL — pattern shows column 5 is active (key pressed)
18. 18. Blank line
19. 19. PHASE 2: Display Update — showing the digit on seven-segment
20. 20. Blank line
21. 21. Code looks up segment pattern for digit 5 from table in RAM
22. 22. CS_RAM activates (memory access, low address range)
23. 23. AL receives 6Dh — the seven-segment pattern that displays '5'
24. 24. Blank line
25. 25. OUT 80h, AL sends the pattern to 8255 Port A (display port)
26. 26. Address bus = 0080h, M/IO=0 for I/O cycle
27. 27. CS_8255 active again, A1=0 A0=0 selects Port A
28. 28. CPU asserts WR, 8255 latches the byte 6Dh onto Port A output pins
29. 29. Seven-segment display lights up segments to show the digit 5
30. 30. Blank line
31. 31. PHASE 3: Serial Logging — send the key value over USART
32. 32. Blank line
33. 33. OUT 60h, AL sends the value to the 8251 data register
34. 34. CS_8251 activates for the I/O address
35. 35. 8251 converts the parallel byte to a serial frame
36. 36. TxD line transmits START bit, 8 data bits, STOP bit at 9600 baud
37. 37. Blank line
38. 38. PHASE 4: Timer Interrupt — asynchronous periodic event
39. 39. Blank line
40. 40. 8254 Counter 0 has been counting down and reaches zero
41. 41. OUT0 output pulses to 8259 IR0 input
42. 42. 8259 sets IRR bit 0, priority resolver selects it, asserts INTR
43. 43. CPU finishes current instruction, sees INTR with IF=1
44. 44. First INTA pulse: 8259 sets ISR bit 0, clears IRR bit 0
45. 45. Second INTA pulse: 8259 places vector 08h on data bus, CPU reads it
46. 46. CPU reads IVT entry at address 0020h — gets ISR address
47. 47. CPU pushes FLAGS, CS, IP onto stack and jumps to TIMER_ISR
48. 48. ISR refreshes the multiplexed display (cycles through digits)
49. 49. ISR sends EOI (20h to port 20h) to clear the 8259 ISR bit
50. 50. IRET pops IP, CS, FLAGS — returns to main loop exactly where it left off
51. 51. Blank line
52. 52. Summary: complete trace from keypress through all chips back to normal execution

Spot the bug

; System ISR for timer interrupt:
;
TIMER_ISR:
  INC WORD PTR [TICK_COUNT]
  CMP WORD PTR [TICK_COUNT], 1000
  JNE TIMER_DONE
  MOV WORD PTR [TICK_COUNT], 0
  ; Send status byte via 8251
  MOV AL, 'T'
  OUT 60h, AL
TIMER_DONE:
  IRET
;
; Main code enables interrupts:
  MOV AL, 0FEh
  OUT 21h, AL           ; unmask IR0
  STI

Explain like I'm 5

Fun fact

Hands-on challenge

More resources

• 8086 System Design Complete Example (Education 4u)
• Microprocessor Exam Questions and Solutions (GeeksforGeeks)
• Tracing 8086 Instructions (Neso Academy)
• 8086 Family User Manual (Intel)