Bus Timing, Ready Signal, and Wait States

Real-world analogy

What is it?

A bus cycle is the sequence of T-states (T1 through T4) the 8086 uses to perform one memory or I/O transfer. T1 outputs the address, T2 sets up control signals, T3 transfers data, and T4 completes the cycle. If the memory or device is too slow, the READY pin inserts wait states (Tw) between T2 and T3 to stretch the cycle.

Real-world relevance

Wait states were a constant battle in early PC design. Fast CPUs paired with slow DRAM needed wait states — an 8 MHz 8086 with 150 ns DRAM might need 1-2 wait states per access. This directly impacted performance. The introduction of cache memory in later processors (386, 486) was specifically to eliminate wait states by keeping frequently accessed data in fast SRAM.

Key points

• T-States: The Clock Subdivisions — Every bus cycle consists of at least 4 clock periods called T1, T2, T3, and T4. Each T-state is one full clock cycle (e.g., at 5 MHz, each T-state is 200 ns). The CPU performs specific actions during each T-state in a predictable sequence.
• T1 — Address Phase — During T1, the 8086 places the 20-bit address on AD0-AD15 and A16-A19. ALE is pulsed HIGH. External latches capture the address on ALE's falling edge. M/IO is set to indicate memory or I/O access. This is the 'here is where I want to go' phase.
• T2 — Control Phase — During T2, the bus transitions from address to data. For a read, AD0-AD15 go to tri-state and RD is asserted. For a write, the CPU places data on AD0-AD15 and asserts WR. DEN enables the data bus transceivers.
• T3 — Data Phase — During T3, the actual data transfer happens. For a read, the addressed memory or I/O device places data on the bus and the CPU samples it. For a write, the memory captures the data from the bus. READY is sampled at the start of T3.
• T4 — Completion Phase — During T4, the bus cycle completes. All control signals are deasserted (RD/WR go HIGH, DEN goes inactive). The data is latched into the CPU register (for reads) or confirmed written (for writes). The bus is then available for the next cycle.
• READY Pin and Wait State Insertion — The READY pin is sampled at the rising edge of T3. If READY is LOW (not ready), the CPU inserts idle Tw states — entire clock cycles where nothing happens. The CPU keeps checking READY each Tw until it goes HIGH, then proceeds to T3.
• Address/Data Multiplexing in Detail — The same 16 wires (AD0-AD15) carry address in T1 and data in T2-T4. The 8282 latch is clocked by ALE to hold the address. The 8286 transceiver is enabled by DEN to buffer the data. This multiplexing is the reason both chips are mandatory.
• Idle States (Ti) — When the CPU has no bus activity (e.g., executing an instruction that does not need memory access), the bus enters idle states (Ti). During Ti, the bus is inactive — no address, no data, no control signals asserted. The BIU may use Ti for prefetch.
• 8284A Clock Generator and READY Synchronization — The 8284A generates the system clock for the 8086 and also synchronizes the READY signal. External slow devices assert their ready signal asynchronously; the 8284A synchronizes it to the 8086 clock to prevent metastability.
• Bus Cycle Timing Calculations — For a 5 MHz 8086, each T-state is 200 ns. A minimum bus cycle (no wait states) takes 4 × 200 = 800 ns. Adding n wait states costs n × 200 ns extra. Memory access time must be less than about 460 ns to avoid wait states at 5 MHz.

Code example

; Complete bus cycle timing for MOV AX, [1000h]
; Assume 5 MHz clock, memory needs 1 wait state

; === T1 (200 ns) ===
; ALE = HIGH
; AD0-AD15 = 1000h (address)
; A16-A19 = segment upper bits
; M/IO = HIGH (memory access)
; ALE falls -> 8282 latches address 1000h

; === T2 (200 ns) ===
; AD0-AD15 go tri-state
; RD asserted LOW
; DEN asserted LOW
; DT/R = LOW (read direction)
; READY sampled -> READY = LOW (memory not ready)

; === Tw (200 ns) — wait state ===
; CPU does nothing, bus held
; READY sampled again -> READY = HIGH (memory ready)

; === T3 (200 ns) ===
; Memory places data on AD0-AD15
; CPU samples data

; === T4 (200 ns) ===
; RD deasserted (HIGH)
; DEN deasserted
; Data latched into AX
; Total: 5T = 1000 ns for this read

Line-by-line walkthrough

1. 1. T1: The address 1000h appears on AD0-AD15 and ALE pulses — the 8282 latch captures and holds this address for the rest of the bus cycle.
2. 2. M/IO = HIGH indicates this is a memory access, not I/O. A16-A19 carry the upper address bits from the segment calculation.
3. 3. T2: AD0-AD15 go tri-state (disconnect from driving address) and RD is pulled LOW — this tells the memory chip to start outputting data.
4. 4. DEN enables the 8286 transceivers and DT/R = LOW sets them to 'receive' direction — data flows from memory toward the CPU.
5. 5. READY is checked: since the memory needs more time, READY is LOW, so the CPU enters a wait state (Tw) instead of proceeding to T3.
6. 6. During Tw, nothing changes on the bus — the CPU just waits. At the end of Tw, READY is sampled again — this time it is HIGH.
7. 7. T3: With READY confirmed HIGH, the memory data is now valid on AD0-AD15 and the CPU samples it.
8. 8. T4: RD goes back HIGH (deasserted), DEN is deasserted, and the data value is latched into AX. Total cycle took 5 T-states = 1000 ns.

Spot the bug

; System: 8086 at 8 MHz with 200 ns memory chips
; Problem: system crashes randomly, data corruption
;
; T-state at 8 MHz = 125 ns
; Bus cycle = 4T = 500 ns
; Memory access time = 200 ns
;
; Designer says: "200 ns < 500 ns, no wait states needed!"
; READY pin is tied permanently to VCC (always ready)
;
; But the system still has data errors...

Explain like I'm 5

Fun fact

Hands-on challenge

More resources

• 8086 Bus Timing Diagrams (GeeksforGeeks)
• 8086 Bus Cycle Timing Explained (YouTube)
• Wait States and Memory Timing (TutorialsPoint)
• 8284A Clock Generator (GeeksforGeeks)