Reset, HOLD, HLDA, and Basic Control Signals

Real-world analogy

What is it?

The 8086's control signals manage system initialization (RESET sets CS=FFFFh, IP=0000h so execution begins at FFFF0h), bus sharing (HOLD/HLDA handshake lets DMA controllers take over the bus for direct memory transfers), interrupt handling (INTA acknowledges hardware interrupts), coprocessor synchronization (TEST/WAIT), and bus locking (LOCK for atomic operations).

Real-world relevance

Every time you power on or restart your computer, the CPU goes through a RESET sequence almost identical to the 8086's — modern x86 processors still start at a high address in the firmware (UEFI/BIOS) ROM. DMA transfers, pioneered with the 8086's HOLD/HLDA mechanism, are still fundamental — your disk controller, network card, and GPU all use DMA to transfer data to RAM without burdening the CPU.

Key points

• RESET Sequence — When RESET is held HIGH for at least 4 clock cycles, the 8086 stops all activity. On RESET going LOW, the CPU initializes: CS=FFFFh, IP=0000h, Flags=0000h, DS=ES=SS=0000h. The first instruction is fetched from physical address FFFF0h.
• The Reset Vector at FFFF0h — Since FFFF0h is only 16 bytes from the end of the 1 MB address space, there is not enough room for the full BIOS code. The first instruction at FFFF0h is typically a FAR JMP to the actual BIOS entry point lower in the ROM address space.
• RESET Pin Electrical Requirements — RESET must be held HIGH for a minimum of 4 clock cycles to guarantee proper initialization. The 8284A clock generator provides a synchronized RESET output from its RES input. During RESET, all bus outputs are tri-stated and the instruction queue is flushed.
• HOLD — Bus Request Input — The HOLD pin is an input to the 8086, asserted by a DMA controller (like 8237) or another bus master to request control of the system bus. The CPU checks HOLD at the end of each bus cycle — it will not stop mid-cycle.
• HLDA — Hold Acknowledge Output — After detecting HOLD=HIGH and finishing the current bus cycle, the 8086 asserts HLDA (HIGH) to signal that it has released the bus. All address, data, and control lines go tri-state. The DMA controller can now directly access memory.
• DMA Bus Release — When the DMA controller finishes its transfer, it deasserts HOLD (LOW). The 8086 sees HOLD=LOW, deasserts HLDA, reclaims the bus, and resumes normal operation from where it left off. No instruction state is lost.
• INTA — Interrupt Acknowledge — INTA is an output asserted during interrupt acknowledge bus cycles. When the CPU accepts an interrupt on INTR, it runs two INTA cycles. The first is a notification; the second tells the interrupt controller (8259A) to place the interrupt vector number on the data bus.
• TEST Pin and WAIT Instruction — The TEST pin is an input checked by the WAIT (or FWAIT) instruction. If TEST=LOW, the CPU continues. If TEST=HIGH, the CPU idles until TEST goes LOW. This is used to synchronize with the 8087 coprocessor — WAIT checks if the 8087 is still busy.
• LOCK Output — LOCK is asserted (LOW) during execution of any instruction prefixed with LOCK. It prevents other bus masters from gaining control of the bus — HOLD requests are not honored during a LOCKed instruction. Essential for atomic read-modify-write operations.
• Control Signal Summary Table — Each control signal has a specific role: RESET initializes, HOLD/HLDA arbitrate the bus, INTA acknowledges interrupts, TEST synchronizes with coprocessors, and LOCK ensures atomicity. Together they form the handshake protocol between the CPU and external hardware.

Code example

; Complete power-on boot sequence of an 8086 system

; === PHASE 1: RESET ===
; Power supply stabilizes, 8284A holds RESET HIGH
; After 4+ clock cycles, RESET goes LOW
; CPU state after RESET:
;   CS=FFFFh, IP=0000h -> fetch from FFFF0h
;   DS=ES=SS=0000h, SP=0000h
;   Flags=0000h (IF=0, interrupts disabled)

; === PHASE 2: First instruction fetch ===
; Physical address = FFFFh << 4 + 0000h = FFFF0h
; ROM at FFFF0h contains:
    JMP FAR F000h:E05Bh  ; Jump to BIOS

; === PHASE 3: BIOS initialization ===
; CS=F000h, IP=E05Bh
; BIOS code initializes hardware:
    CLI                   ; Ensure interrupts off
    MOV AX, 0000h
    MOV DS, AX           ; DS = 0000h
    MOV SS, AX           ; SS = 0000h
    MOV SP, 0400h        ; Set up stack

; === PHASE 4: Hardware test and setup ===
; BIOS tests RAM, initializes 8259A, 8253, etc.
; Sets up interrupt vector table at 0000:0000
; Eventually enables interrupts:
    STI                   ; IF=1, INTR now active

; === PHASE 5: Boot ===
; BIOS loads boot sector from disk via DMA:
;   8237 DMA asserts HOLD
;   CPU asserts HLDA, releases bus
;   DMA reads disk data directly to RAM at 7C00h
;   DMA releases HOLD
;   CPU resumes, JMPs to 0000:7C00h (boot sector)

Line-by-line walkthrough

1. 1. After RESET releases, CS=FFFFh and IP=0000h. The physical address is FFFFh shifted left 4 bits plus 0000h = FFFF0h. ROM must be mapped here.
2. 2. JMP FAR F000h:E05Bh at FFFF0h loads CS with F000h and IP with E05Bh — this jumps to the actual BIOS code further down in ROM.
3. 3. CLI clears the Interrupt Flag — we do not want interrupts firing before the interrupt vector table and hardware are initialized.
4. 4. MOV AX,0000h then MOV DS/SS,AX sets the data and stack segments to zero — segment registers cannot be loaded with immediate values directly.
5. 5. MOV SP,0400h sets up the stack pointer so PUSH, POP, CALL, and interrupts have a valid stack to use.
6. 6. BIOS code then tests RAM, initializes peripheral chips (8259A interrupt controller, 8253 timer, 8237 DMA), and builds the interrupt vector table.
7. 7. STI enables interrupts once everything is set up — now the 8259A can deliver hardware interrupts to the CPU via INTR.
8. 8. The DMA sequence: 8237 asserts HOLD, CPU finishes its current cycle and asserts HLDA, bus goes tri-state, DMA reads disk sector directly to RAM at 7C00h, DMA releases HOLD, CPU deasserts HLDA and resumes.
9. 9. Finally the BIOS jumps to 0000:7C00h where the boot sector code now resides in RAM — the operating system loading process begins.

Spot the bug

; After RESET, the system hangs — never reaches BIOS
; Hardware setup:
;   ROM chip mapped at address range F0000h-FFFFFh
;   RAM chip mapped at address range 00000h-0FFFFh
;   No other memory chips installed
;
; ROM contents at offset FFF0h (physical FFFF0h):
;   JMP FAR 0000h:8000h  ; Jump to RAM at 08000h
;
; Observation: CPU fetches first instruction OK
; but hangs immediately after the JMP

Explain like I'm 5

Fun fact

Hands-on challenge

More resources

• 8086 Reset and Startup (GeeksforGeeks)
• HOLD/HLDA and DMA in 8086 (YouTube)
• x86 Boot Process from RESET to OS (TutorialsPoint)
• 8086 Control Signals (JavaTPoint)